Microelectronic elements such as semiconductor chips generate considerable amounts of heat during use. A complex, high-speed chip a few cm.sup.2 in area may produce tens of watts of heat. This heat must be dissipated while maintaining the chip at a safe operating temperature. The heat dissipation problem is even more severe where chips and other components are closely packed in assemblies commonly referred to as "multi-chip modules". Such modules typically incorporate one or more substrates with chips disposed close to one another on the substrate. Improvements in chip mountings and electrical connections, and in related assembly methods, have made it possible to reduce the distance between chips so as to achieve a more compact assembly. With sophisticated assembly techniques, it is possible to fill the entire area of the substrate with chips. The heat dissipation problem is particularly extreme in such compact multi-chip modules.
Considerable effort has been devoted in the art towards meeting these needs for cooling. A general outline of the approaches taken heretofore is set forth in the text Multichip Module Technologies and Alternatives--The Basics, Doane, D. A. and Franzon, P. D., EDS 1993 Van Nostrand Reinhold, New York, N.Y. at chapter 12, pp. 569-613, entitled "Thermal Design Considerations For Multichip Module Applications" (Azar, K., chapter author) and at pages 109-111 of the same reference. As described therein, heat transfer problems in electronic packaging can be addressed in terms of "thermal resistance" of the elements involved. The thermal resistance of any element in the heat transfer path refers to the ratio between the temperature difference across such element and the rate of heat flow through the element. Thermal insulators have high thermal resistance whereas elements which convey heat effectively by conduction or convection have low thermal resistance. The overall thermal resistance of the package is the sum of the individual thermal resistances in series in the heat path between the chip and the ambient environment. The overall thermal resistance in turn provides a ratio between the temperature rise of the chips above ambient temperature and the amount of heat produced in the chips.
As described in the aforementioned reference, the heat conduction pathway may include an element commonly referred to as a "heat sink". There is normally a low thermal resistance connection from the heat sink to the environment. For example, the vanes of the heat sink may be bathed in a flow of forced air or liquid. However, there is generally an appreciable thermal resistance between the chips or after microelectronic components and the heat sink. Stated another way, it is difficult to provide a low thermal resistance connection between the chips, or a subassembly including the chips, and the heat sink while still meeting all of the other requirements for such a connection. The thermal connection must accommodate relative movement between the chips or other components and the heat sink during use of the device. Such relative movement arises in part from movement of the components and the substrate bearing the components as the assembly undergoes temperature changes during use. When the unit is first supplied with power, the temperature of the chips or other components and the substrate rises faster than the temperature of the substrate, causing differential thermal expansion, warpage and distortion. Further, the coefficients of thermal expansion of the chips and the substrate normally are not matched with the coefficient thermal expansion of the heat sink, causing further differential thermal expansion and contraction. Mechanical stresses imposed upon the assembly during handling and installation can cause additional relative movement.
Moreover, the connection between the components and the heat sink should accommodate dimensional tolerances in the components, the substrate and the heat sink itself. For example, the chips themselves may be of different thicknesses. Also, the chips can be supported at different levels above the face of the substrate by solder balls or other mountings. The surfaces of the chips may be tilted from their nominal positions, so that the chip surfaces are out of alignment with the surface of the heat sink. The heat sink itself may not be perfectly flat or parallel to the nominal plane of the chip surfaces. Any elements used to connect the heat sink with the chip or the components should be capable of accommodating these tolerances and misalignments.
Daszkowski, U.S. Pat. Nos. 4,654,754 and 4,689,720 disclose a thermal link using either a metallic spring disposed between the heat sink and the active device or a thermally conductive elastomer which can be crushed between the heat sink and the device without exerting very high forces on the device.
Kajiwara et al, U.S. Pat. No. 4,996,589 discloses a module in which a liquid cooled heat sink is connected to a chip by a low melting solder, the sink itself being equipped with a bellows-like device to allow displacement of the heat sink so as to accommodate tolerances and misalignment.
Turlik et al, U.S. Pat. No. 5,325,265 discloses a multichip module in which chips are bonded to a ceramic support substrate having coefficient of thermal expansion matching that of the chip and the heat sink also has a matching coefficient of expansion. The exposed faces of the chips are connected to the heat sink by a "soft, thermally conductive mechanical cushion material", desirably a low-melting point indium material which is melted in place.
Okada et al, U.S. Pat. No. 5,150,274; Chall, Jr., U.S. Pat. No. 4,858,072 and Ueda et al, U.S. Pat. No. 5,025,307 all disclose chip assemblies using fluid-cooled heat sinks. Watson et al, U.S. Pat. No. 5,168,926 discloses a chip assembly in which a heat sink is attached to the chip carrier by a thermally conductive adhesive after the chip carrier is soldered to a larger circuit board.
Horvath et al, U.S. Pat. Nos. 5,052,481 and 5,014,117 disclose arrangements for connecting multiple chips to a common heat sink having a slotted face using mating slotted elements and flexible metallic elements attached to the chips and to the heat sinks or both. These elements interfit with one another to provide a thermal path between the chips and the heat sink.
Mittal, U.S. Pat. No. 4,485,429 describes a cooling arrangement in which bunches of heat conducting strands extend from chips to a housing which in turn is bathed in a fluid. The housing may have further strands attached to it to promote heat dissipation into the fluids. The strands are said to be flexible. Funari et al, U.S. Pat. No. 4,849,856 discloses a heat sink with flexible feet so that the heat sink can be forced downwardly against a chip without damaging the chip.
Chu et al, U.S. Pat. No. 4,156,458 discloses a multi-chip module incorporating bundles of metallic foils extending between the microelectronic element and the heat sink. The ends of the foils adjacent the microelectronic elements are "microsliced" or cut into thin, individual ribbons so that the same are "better able to flex and follow any minute contours of the chip surface and also slight tilt of the chip surface".
Dobear et al, U.S. Pat. No. 4,993,482 describes the use of thermally conductive coil springs disposed between the chip and the heat sink. Bellar et al, U.S. Pat. No. 5,270,902; Horvath, U.S. Pat. No. 4,415,025 and Horvath et al, U.S. Pat. No. 5,159,531 all disclose arrangements in which a dome-like sheet metal element with multiple cuts therein is disposed between each chip and the associated heat sink, or in which several such elements are nested within one another to provide multiple heat paths.
Reynolds, U.S. Pat. No. 5,206,792 describes a further sheet metal element for connecting a chip to a heat sink, the sheet metal element including numerous mechanically compliant fingers at its periphery.
Despite all of this effort in the art, further improvement in thermal conductive elements and in assemblies incorporating the same is still desired. In particular, it is difficult to achieve a low thermal resistance connection between the chip or other microelectronic element and the heat sink while still providing the required compliance to take up tolerances and movement due to thermal effects. Moreover, many of the prior solutions have required costly and failure-prone manufacturing steps.